The present invention relates to computer architectures and in particular to a computer and memory system providing both parallel and serial buses for communicating between processors and memory.
Modern computer processors can process data faster than the data can be exchanged with external memory. For this reason, there is considerable interest in increasing the “bandwidth” of the memory bus communicating between processors and external memory so that faster data transfers can occur and processor speed may be better utilized.
The bandwidth of a memory bus is a function both of the transmission speed of the memory bus (the number of bits that can be transmitted per second) and the width of the memory bus (the number of bits that can be transmitted simultaneously). Typical memory buses are parallel buses employing multiple conductors that simultaneously transmit multiple bits of data words at a high bit rate. A data word is the unit of data (number of bits) that the processor can simultaneously process.
Increasing the bandwidth of a memory bus can be obtained by increasing transmission speed or memory bus width. Increasing the memory bus width, or number of parallel conductors in the memory bus, is practically limited by constraints in the number of pins (terminals) that can be physically added to processor and memory integrated circuit packages. Currently over 130 I/O pins are required for DDR3 (double data rate type iii synchronous dynamic random access memory).
Increasing the speed of each parallel conductor is limited by degradation of the transmitted data resulting from increased crosstalk between parallel data lines and attenuation of the signal at high speeds. To some extent, these signal degradation problems can be addressed by increasing transmission power but at the cost of greatly increasing power usage that rises disproportionately (super linearly) to speed increases. Increasing the speed of the memory bus also causes a skewing or phase shifting of the data transmitted on separate parallel conductors with respect to the common clock, introducing errors in reconstructing the data at the end of the bus.